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| ? 2008 microchip technology inc. ds21227f-page 1 25aa320/25lc320/25c320 device selection table features: low-power cmos technology: - write current: 3 ma maximum - read current: 500 a, typical - standby current: 500 na, typical 4096 x 8 bit organization 32 byte page write cycle time: 5 ms maximum self-timed erase and write cycles block write protection: - protect none, 1/4, 1/2 or all of array built-in write protection: - power on/off data protection circuitry - write enable latch - write-protect pin sequential read high reliability: - endurance: 1m e/w cycles - data retention: > 200 years - esd protection: > 4000v 8-pin pdip, soic and tssop packages 14-lead tssop package temperature ranges supported: description: the microchip technology inc. 25aa320/25lc320/ 25c320 (25xx320 * ) are 32 kbit serial electrically erasable proms. the memory is accessed via a simple serial peripheral interface (spi) compatible serial bus. the bus signals required are a clock input (sck) plus separate data in (si) and data out (so) lines. access to the device is controlled through a chip select (cs ) input. communication to the device can be paused via the hold pin (hold ). while the device is paused, transitions on its inputs will be ignored, with the exception of chip select, allowing the host to service higher priority interrupts. block diagram package types part number v cc range max. clock frequency temp. ranges 25aa320 1.8-5.5v 1 mhz i 25lc320 2.5-5.5v 2 mhz i,e 25c320 4.5-5.5v 3 mhz i,e - industrial (i): -40 cto +85 c - automotive (e): -40c to +125c si so sck cs hold wp status register i/o control memory control logic hv generator eeprom array page y decoder sense amp. r/w control logic v cc v ss latches xdec tssop pdip, soic tssop cs so wp v ss v cc hold sck si 12 3 4 87 6 5 25xx320 hold v cc cs so 12 3 4 87 6 5 scksi v ss wp 25xx320 nc cs sonc wp v ss nc nc v cc hold ncsck si nc 25xx320 12 3 4 1413 12 11 51 0 9 78 6 32k spi bus serial eeprom *25xx320 is used in this docum ent as a generic part number fo r the 25aa320/25lc320/25c320 devices. not recommended for new designs C please use 25aa320a or 25lc320a. downloaded from: http:///
25aa320/25lc320/25c320 ds21227f-page 2 ? 2008 microchip technology inc. 1.0 electrical characteristics absolute maximum ratings (?) v cc .............................................................................................................................................................................7.0v all inputs and outputs w.r.t. v ss ........................................................................................................ -0.6v to v cc + 1.0v storage temperature ............................................................................................................ .....................-65c to 150c ambient temperature under bias ................................................................................................. ..............-40c to 125c esd protection on all pins ..................................................................................................... .....................................4 kv table 1-1: dc characteristics ? notice : stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. exposure to maximum rating conditions for a n extended period of time may affect device reliability. dc characteristics industrial (i): t a = -40c to +85c v cc = 1.8v to 5.5v automotive (e):t a = -40c to +125c v cc = 2.5v to 5.5v param. no. sym. characteristics min. max. units conditions d1 v ih 1 high-level input voltage 2.0 v cc +1 v v cc 2.7v (note) d2 v ih 2 0.7 v cc v cc +1 v v cc < 2.7v (note) d3 v il 1 low-level input voltage -0.3 0.8 v v cc 2.7v (note) d4 v il 2 -0.3 0.3 v cc vv cc < 2.7v (note) d5 v ol low-level output voltage 0 . 2v i ol = 1.0 ma, v cc < 2.5v d6 v oh high-level output voltage v cc -0.5 v i oh = -400 a d7 i li input leakage current 1 acs = v cc , v in = v ss to v cc d8 i lo output leakage current 1 acs = v cc , v out = v ss to v cc d9 c int internal capacitance (all inputs and outputs) 7p f t a = 25c, clk = 1.0 mhz, v cc = 5.0v (note) d10 i cc read operating current 1 500 ma a v cc = 5.5v; f clk = 3.0 mhz; so = open v cc = 2.5v; f clk = 2.0 mhz; so = open d11 i cc write 53 mama v cc = 5.5v v cc = 2.5v d12 i ccs standby current 51 a a cs = v cc = 5.5v, inputs tied to v cc or v ss cs = v cc = 2.5v, inputs tied to v cc or v ss note: this parameter is periodically sampled and not 100% tested. downloaded from: http:/// ? 2008 microchip technology inc. ds21227f-page 3 25aa320/25lc320/25c320 table 1-2: ac characteristics ac characteristics industrial (i): t a = -40c to +85c v cc = 1.8v to 5.5v automotive (e): t a = -40c to +125c v cc = 2.5v to 5.5v param. no. sym. characteristic min. max. units conditions 1f clk clock frequency 32 1 mhz mhz mhz v cc = 4.5v to 5.5v v cc = 2.5v to 5.5v v cc = 1.8v to 5.5v 2t css cs setup time 100 250500 nsns ns v cc = 4.5v to 5.5v v cc = 2.5v to 5.5v v cc = 1.8v to 5.5v 3t csh cs hold time 150 250475 nsns ns v cc = 4.5v to 5.5v v cc = 2.5v to 5.5v v cc = 1.8v to 5.5v 4t csd cs disable time 500 ns 5t su data setup time 30 5050 nsns ns v cc = 4.5v to 5.5v v cc = 2.5v to 5.5v v cc = 1.8v to 5.5v 6t hd data hold time 50 100100 nsns ns v cc = 4.5v to 5.5v v cc = 2.5v to 5.5v v cc = 1.8v to 5.5v 7t r clk rise time 2 s (note 1) 8t f clk fall time 2 s (note 1) 9t hi clock high time 150 230475 nsns ns v cc = 4.5v to 5.5v v cc = 2.5v to 5.5v v cc = 1.8v to 5.5v 10 t lo clock low time 150 230475 nsns ns v cc = 4.5v to 5.5v v cc = 2.5v to 5.5v v cc = 1.8v to 5.5v 11 t cld clock delay time 50 ns 12 t cle clock enable time 50 ns 13 t v output valid from clock low 150230 nsns ns v cc = 4.5v to 5.5v v cc = 2.5v to 5.5v v cc = 1.8v to 5.5v 14 t ho output hold time 0 ns (note 1) 15 t dis output disable time 200250 nsns ns v cc = 4.5v to 5.5v (note 1) v cc = 2.5v to 5.5v (note 1) v cc = 1.8v to 5.5v 16 t hs hold setup time 100 100200 nsns ns v cc = 4.5v to 5.5v v cc = 2.5v to 5.5v v cc = 1.8v to 5.5v 17 t hh hold hold time 100 100200 nsns ns v cc = 4.5v to 5.5v v cc = 2.5v to 5.5v v cc = 1.8v to 5.5v 18 t hz hold low to output high-z 100150 200 nsns ns v cc = 4.5v to 5.5v (note 1) v cc = 2.5v to 5.5v (note 1) v cc = 1.8v to 5.5v 19 t hv hold high to output valid 100150 200 nsns ns v cc = 4.5v to 5.5v v cc = 2.5v to 5.5v v cc = 1.8v to 5.5v 20 t wc internal write cycle time 5m s 21 endurance 1m e/w cycles (note 2) note 1: this parameter is periodically sampled and not 100% tested. 2: this parameter is not tested but established by characteri zation. for endurance estimates in a specific application, please consult the total endurance? model which can be obta ined from microchips web site at: www.microchip.com. downloaded from: http:/// 25aa320/25lc320/25c320 ds21227f-page 4 ? 2008 microchip technology inc. figure 1-1: hold timing figure 1-2: serial input timing figure 1-3: serial output timing cs sck so si hold 17 16 16 17 19 18 dont care 5 high-impedance n + 2 n + 1 n n - 1 n n + 2 n + 1 n n n - 1 cs sck si so 6 5 8 7 11 3 lsb in msb in high-impedance 12 mode 1 , 1 mode 0 , 0 4 2 cs sck so 10 9 13 msb out isb out 3 15 dont care si mode 1 , 1 mode 0 , 0 14 downloaded from: http:/// ? 2008 microchip technology inc. ds21227f-page 5 25aa320/25lc320/25c320 table 1-3: ac test conditions f igure 1-4: ac test circuit ac waveform: v lo = 0.2v v hi = v cc - 0.2v (note 1) v hi = 4.0v (note 2) timing measurement reference level input 0.5 v cc output 0.5 v cc note 1: for v cc 4.0v 2: for v cc > 4.0v v cc so 100 pf 1.8 k 2.25 k downloaded from: http:/// 25aa320/25lc320/25c320 ds21227f-page 6 ? 2008 microchip technology inc. 2.0 pin descriptions the descriptions of the pins are listed in table 2-1. table 2-1: pin function table 2.1 chip select (cs ) a low level on this pin selects the device. a high level deselects the device and forces it into standby mode. however, a programming cycle which is already initiated or in progress will be completed, regardless of the cs input signal. if cs is brought high during a program cycle, the device will go into standby mode as soon as the programming cycle is complete. when the device is deselected, so goes to the high-impedance state, allowing multiple parts to share the same spi bus. a low-to-high transition on cs after a valid write sequence initiates an internal write cycle. after power- up, a low level on cs is required prior to any sequence being initiated. 2.2 serial output (so) the so pin is used to transfer data out of the 25xx320. during a read cycle, data is shifted out on this pin after the falling edge of the serial clock. 2.3 write-protect (wp ) this pin is used in conjunction with the wpen bit in the status register to prohibit writes to the nonvolatile bits in the status register. when wp is low and wpen is high, writing to the nonvolatile bits in the sta- tus register is disabled. all other operations function normally. when wp is high, all functions, including writes to the nonvolatile bits in the status register operate normally. if the wpen bit is set, wp low during a status register write sequence will disable writing to the status register. if an internal write cycle has already begun, wp going low will have no effect on the write. the wp pin function is blocked when the wpen bit in the status register is low. this allows the user to install the 25xx320 in a system with wp pin grounded and still be able to write to the status register. the wp pin functions will be enabled when the wpen bit is set high. 2.4 serial input (si) the si pin is used to transfer data into the device. it receives instructions, addresses, and data. data is latched on the rising edge of the serial clock. 2.5 serial clock (sck) the sck is used to synchronize the communication between a master and the 25xx320. instructions, addresses, or data present on the si pin are latched on the rising edge of the clock input, while data on the so pin is updated after the falling edge of the clock input. 2.6 hold (hold ) the hold pin is used to suspend transmission to the 25xx320 while in the middle of a serial sequence with- out having to re-transmit the entire sequence again. it must be held high any time this function is not being used. once the device is selected and a serial sequence is underway, the hold pin may be pulled low to pause further serial communication without resetting the serial sequence. the hold pin must be brought low while sck is low, otherwise the hold function will not be invoked until the next sck high-to- low transition. the 25xx320 must remain selected dur- ing this sequence. the si, sck, and so pins are in a high-impedance state during the time the device is paused and transitions on these pins will be ignored. to resume serial communication, hold must be brought high while the sck pin is low, otherwise serial communication will not resume. lowering the hold line at any time will tri-state the so line. name pdip soic 8-pin tssop 14-lead tssop description cs 1 1 3 1 chip select input so 2 2 4 2 serial data output nc 3,4,5 not connected wp 3 3 5 6 write-protect pin vss 4 4 6 7 ground si 5 5 7 8 serial data input sck 6 6 8 9 serial clock input nc 10,11,12 not connected hold 7 7 1 13 hold input vcc 8 8 2 14 supply voltage downloaded from: http:/// ? 2008 microchip technology inc. ds21227f-page 7 25aa320/25lc320/25c320 3.0 functional description 3.1 principles of operation the 25xx320 are 4096 byte serial eeproms designed to interface directly with the serial peripheral interface (spi) port of many of todays popular microcontroller families, including microchips pic16c6x/7x microcontrollers. it may also interface with microcontrollers that do not have a built-in spi port by using discrete i/o lines programmed properly with the software. the 25xx320 contains an 8-bit instruction register. the device is accessed via the si pin, with data being clocked in on the rising edge of sck. the cs pin must be low and the hold pin must be high for the entire operation. table 3-1 contains a list of the possible instruction bytes and format for device operation. all instructions, addresses and data are transferred msb first, lsb last. data is sampled on the first rising edge of sck after cs goes low. if the clock line is shared with other peripheral devices on the spi bus, the user can assert the hold input and place the 25xx320 in hold mode. after releasing the hold pin, operation will resume from the point when the hold was asserted. 3.2 read sequence the device is selected by pulling cs low. the 8-bit read instruction is transmitted to the 25xx320 fol- lowed by the 16-bit address, with the four msbs of the address being dont care bits. after the correct read instruction and address are sent, the data stored in the memory at the selected address is shifted out on the so pin. the data stored in the memory at the next address can be read sequentially by continuing to pro- vide clock pulses. the internal address pointer is auto- matically incremented to the next higher address after each byte of data is shifted out. when the highest address is reached (0fffh), the address counter rolls over to address 0000h allowing the read cycle to be continued indefinitely. the read operation is terminated by raising the cs pin (figure 3-1). 3.3 write sequence prior to any attempt to write data to the 25xx320, the write enable latch must be set by issuing the wren instruction (figure 3-4). this is done by setting cs low and then clocking out the proper instruction into the 25xx320. after all eight bits of the instruction are transmitted, the cs must be brought high to set the write enable latch. if the write operation is initiated immediately after the wren instruction without cs being brought high, the data will not be written to the array because the write enable latch will not have been properly set. once the write enable latch is set, the user may proceed by setting the cs low, issuing a write instruction, followed by the 16-bit address, with the four msbs of the address being dont care bits, and then the data to be written. up to 32 bytes of data can be sent to the 25xx320 before a write cycle is necessary. the only restriction is that all of the bytes must reside in the same page. a page address begins with xxxx xxxx xxx0 0000 and ends with xxxx xxxx xxx1 1111 . if the internal address counter reaches xxxx xxxx xxx1 1111 and the clock continues, the counter will roll back to the first address of the page and over- write any data in the page that may have been written. for the data to be actually written to the array, the cs must be brought high after the least significant bit (d0) of the n th data byte has been clocked in. if cs is brought high at any other time, the write operation will not be completed. refer to figure 3-2 and figure 3-3 for more detailed illustrations on the byte write sequence and the page write sequence, respectively. while the write is in progress, the status register may be read to check the status of the wpen, wip, wel, bp1 and bp0 bits (figure 3-6). a read attempt of a memory array location will not be possible during a write cycle. when the write cycle is completed, the write enable latch is reset. table 3-1: instruction set instruction name instruction format description read 0000 0011 read data from memory array beginning at selected address write 0000 0010 write data to memory array beginning at selected address wrdi 0000 0100 reset the write enable latch (disable write operations) wren 0000 0110 set the write enable latch (enable write operations) rdsr 0000 0101 read status register wrsr 0000 0001 write status register downloaded from: http:/// 25aa320/25lc320/25c320 ds21227f-page 8 ? 2008 microchip technology inc. figure 3-1: read sequence figure 3-2: byte write sequence figure 3-3: page write sequence so si sck cs 0 234567891011 21222324252627282930 31 1 01 0 0 0 0 01 15 14 13 12 210 76543210 instruction 16-bit address data out high-impedance so si cs 9 1011 21222324252627282930 31 00 0 0 0 0 01 15 14 13 12 210 76543210 instruction 16-bit address data byte high-impedance sck 0 234567 18 twc si cs 9 1011 21222324252627282930 31 00 0 0 0 0 01 15 14 13 12 210 76543210 instruction 16-bit address data byte 1 sck 0 234567 18 si cs 41 42 43 46 47 76543210 data byte n (32 max) sck 32 34 35 36 37 38 39 33 40 76543210 data byte 3 76543210 data byte 2 44 45 downloaded from: http:/// ? 2008 microchip technology inc. ds21227f-page 9 25aa320/25lc320/25c320 3.4 write enable ( wren ) and write disable ( wrdi ) the 25xx320 contains a write enable latch. see table 3-3 for the write-protect functionality matrix. this latch must be set before any write operation will be completed internally. the wren instruction will set the latch, and the wrdi will reset the latch. the following is a list of conditions under which the write enable latch will be reset: power-up wrdi instruction successfully executed wrsr instruction successfully executed write instruction successfully executed figure 3-4: write enable sequence figure 3-5: write disable sequence sck 0 234567 1 si high-impedance so cs 01 0000 0 1 sck 0 234567 1 si high-impedance so cs 01 0000 0 1 0 downloaded from: http:/// 25aa320/25lc320/25c320 ds21227f-page 10 ? 2008 microchip technology inc. 3.5 read status register instruction ( rdsr ) the read status register instruction ( rdsr ) provides access to the status register. the status register may be read at any time, even during a write cycle. the status register is formatted as follows: the write-in-process (wip) bit indicates whether the 25xx320 is busy with a write operation. when set to a 1 , a write is in progress; when set to a 0 , no write is in progress. this bit is read-only. the write enable latch (wel) bit indicates the status of the write enable latch. when set to a 1 , the latch allows writes to the array, when set to a 0 , the latch prohibits writes to the array. the state of this bit can always be updated via the wren or wrdi commands regardless of the state of write protection on the sta- tus register. this bit is read-only. the block protection (bp0 and bp1) bits indicate which blocks are currently write-protected. these bits are set by the user issuing the wrsr instruction. these bits are nonvolatile. see figure 3-6 for the rdsr timing sequence. figure 3-6: read status register timing sequence 76543 2 1 0 wpen x x x bp1 bp0 wel wip so si cs 91011 12131415 11 0 0 0 0 00 7654 2 10 instruction data from status register high-impedance sck 0 234567 1 8 3 downloaded from: http:/// ? 2008 microchip technology inc. ds21227f-page 11 25aa320/25lc320/25c320 3.6 write status register instruction ( wrsr ) the write status register instruction ( wrsr ) allows the user to select one of four levels of protection for the array by writing to the appropriate bits in the status register. the array is divided up into four segments. the user has the ability to write-protect none, one, two, or all four of the segments of the array. the partitioning is controlled as shown in table 3-2. the write-protect enable (wpen) bit is a nonvolatile bit that is available as an enable bit for the wp pin. the write-protect (wp ) pin and the write-protect enable (wpen) bit in the status register control the pro- grammable hardware write-protect feature. hardware write protection is enabled when wp pin is low and the wpen bit is high. hardware write protection is disabled when either the wp pin is high or the wpen bit is low. when the chip is hardware write-protected, only writes to nonvolatile bits in the status register are disabled. see table 3-3 for a matrix of functionality on the wpen bit. see figure 3-7 for the wrsr timing sequence. table 3-2: array protection figure 3-7: write status register timing sequence bp1 bp0 array addresses write-protected 00 none 01 upper 1/4 (0c00h-0fffh) 10 upper 1/2 (0800h-0fffh) 11 all (0000h-0fffh) so si cs 91011 12131415 01 0 0 0 0 00 7654 210 instruction data to status register high-impedance sck 0 234567 1 8 3 downloaded from: http:/// 25aa320/25lc320/25c320 ds21227f-page 12 ? 2008 microchip technology inc. 3.7 data protection the following protection has been implemented to prevent inadvertent writes to the array: the write enable latch is reset on power-up a write enable instruction must be issued to set the write enable latch after a byte write, page write or status register write, the write enable latch is reset cs must be set high after the proper number of clock cycles to start an internal write cycle access to the array during an internal write cycle is ignored and programming is continued 3.8 power-on state the 25xx320 powers on in the following state: the device is in low-power standby mode (cs = 1 ) the write enable latch is reset so is in high-impedance state a low level on cs is required to enter active state . table 3-3: write-protec t functionality matrix wpen wp wel protected blocks unprotected blocks status register xx0 protected protected protected 0x1 protected writable writable 1 low 1 protected writable protected x high 1 protected writable writable downloaded from: http:/// ? 2008 microchip technology inc. ds21227f-page 13 25aa320/25lc320/25c320 4.0 packaging information 4.1 package marking information xxxxxxxx xxxxxnnn yyww 8-lead pdip (300 mil) example: 14-lead tssop example: 8-lead soic (150 mil) example: xxxxxxxx xxxxyyww nnn xxxxxxxx nnn 25lc320 /pnnn yyww 25lc320 i/sn yyww nnn 25l32 yyww nnn 8-lead tssop example: xxxx xyww nnn 5lbx iyww nnn yyww * standard marking consists of microchip part number, year code, week code, and traceability code. for device markings beyond this, certain price adders apply. please check with your microchip sales office. for qtp devices, any special marking adders are included in qtp price. legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week 01) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e 3 e downloaded from: http:/// 25aa320/25lc320/25c320 ds21227f-page 14 ? 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""#$%& !' 3 & ' !&" & 4 # *!( !!& 4 % & &# & && 255***' '5 4 downloaded from: http:/// ? 2008 microchip technology inc. ds21227f-page 17 25aa320/25lc320/25c320 () )" * ! (+%+ ( ! !" #$% &" ' ()"&'"!&) &#*& & & # '! ! #. # &"#' #% ! & "! ! #% ! & "! !! &$# '' !# - '! #& .0 1,2 1 !'! & $ & "! **& "&& ! .32 % '! ("!" *& "&& (% % ' & " !! 3 & ' !&" & 4 # *!( !!& 4 % & &# & && 255***' '5 4 6&! 99. . '! 9'&! 7 7: ; 7"') % ! 7 < & ? 1, : 8 & = = ## 4 4!! < & # %% = : >#& . ?1, ## 4 >#& . - ## 4 9& - - 3 &9& 9 ? 3 & & 9 .3 3 & b = #& ) = - d n e e1 note 1 12 b e c a a1 a2 l1 l * , 25aa320/25lc320/25c320 ds21227f-page 18 ? 2008 microchip technology inc. ,+ () )" * ! (+%+ ( ! !" #$% &" ' ()"&'"!&) &#*& & & # '! ! #. # &"#' #% ! & "! ! #% ! & "! !! &$# '' !# - '! #& .0 1,2 1 !'! & $ & "! **& "&& ! .32 % '! ("!" *& "&& (% % ' & " !! 3 & ' !&" & 4 # *!( !!& 4 % & &# & && 255***' '5 4 6&! 99. . '! 9'&! 7 7: ; 7"') % ! 7 & ? 1, : 8 & = = ## 4 4!! < & # %% = : >#& . ?1, ## 4 >#& . - ## 4 9& 3 &9& 9 ? 3 & & 9 .3 3 & b = #& ) = - note 1 d n e e1 1 2 e b c a a1 a2 l1 l * ,<1 downloaded from: http:/// ? 2008 microchip technology inc. ds21227f-page 19 25aa320/25lc320/25c320 appendix a: revision history revision d corrections to section 1.0, electrical characteristics. revision e revise endurance from 100k to 1m. revision f (june 2008) added not recommended note; updated packaging; general updates. downloaded from: http:/// 25aa320/25lc320/25c320 ds21227f-page 20 ? 2008 microchip technology inc. notes: downloaded from: http:/// ? 2008 microchip technology inc. ds21227f-page 21 25aa320/25lc320/25c320 the microchip web site microchip provides online support via our www site at www.microchip.com. this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: product support C data sheets and errata, application notes and sample programs, design resources, users guides and hardware support documents, latest software releases and archived software general technical support C frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing business of microchip C product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchips customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com, click on customer change notification and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: distributor or representative local sales office field application engineer (fae) technical support development systems information line customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this document. technical support is available through the web site at: http://support.microchip.com downloaded from: http:/// 25aa320/25lc320/25c320 ds21227f-page 22 ? 2008 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microc hip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our document ation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this docume nt. to : technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds21227f 25aa320/25lc320/25c320 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you think would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document? downloaded from: http:/// ? 2008 microchip technology inc. ds21227f-page 23 25aa320/25lc320/25c320 product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . part no. x /xx xxx pattern package temperature range device device: 25aa320: 32 kbit 1.8v spi serial eeprom 25aa320t: 32 kbit 1.8v spi serial eeprom (tape and reel) 25aa320x 32-bit 1.8v spi serial eeprom in alternate pinout (st only) 25aa320xt 32-bit 1.8v spi serial eeprom in alternate pinout tape and reel (st only) 25lc320: 32 kbit 2.5v spi serial eeprom 25lc320t: 32 kbit 2.5v spi serial eeprom (tape and reel) 25lc320x 32-bit 2.5v spi serial eeprom in alternate pinout (st only) 25lc320xt 32-bit 2.5v spi serial eeprom in alternate pinout tape and reel (st only) 25c320: 32 kbit 5v spi serial eeprom 25c320t: 32 kbit 5v spi serial eeprom (tape and reel) 25c320x 32-bit 5v spi serial eeprom in alternate pinout (st only) 25c320xt 32-bit 5v spi serial eeprom in alternate pinout tape and reel (st only) temperature range: i= - 4 0 c to +85 c e= - 4 0 c to +125 c package: p = plastic dip (300 mil body), 8-lead sn = plastic soic (150 mil body), 8-lead st = plastic tssop (4.4 mm body), 8-lead st14 = plastic tssop (4.4 mm body), 14-lead examples: a) 25lc320-i/sn: industrial temp., soic package b) 25lc320t-i/sn: tape and reel, industrial temp., soic package c) 25lc320-e/sn: extended temp., soic package d) 25c320-i/sn: industrial temp., soic package e) 25c320t-i/sn: tape and reel, industrial temp., soic package f) 25c320-i/st: industrial temp., tssop package g) 25c320-e/sn: extended temp., soic package downloaded from: http:/// 25aa320/25lc320/25c320 ds21227f-page 24 ? 2008 microchip technology inc. notes: downloaded from: http:/// ? 2008 microchip technology inc. ds21227f-page 25 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyers risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pro mate, rfpic and smartshunt are registered trademarks of microchip tec hnology incorporated in the u.s.a. and other countries. filterlab, linear active thermistor, mxdev, mxlab, seeval, smartsensor and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, appl ication maestro, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, in-circuit serial programming, icsp, icepic, mindi, miwi, mpasm, mplab certified logo, mplib, mplink, mtouch, pickit, picdem, picdem.net, pictail, pic 32 logo, powercal, powerinfo, powermate, powertool, real ice, rflab, select mode, total endurance, uni/o, wiperlock and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2008, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: microchip products meet the specification cont ained in their particular microchip data sheet. microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip products in a manner outside the operating specif ications contained in microchips data sheets. most likely, the person doing so is engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as unbreakable. code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchips code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the companys quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory an d analog products. in addition, microchips quality system for the design and manufacture of development systems is iso 9001:2000 certified. downloaded from: http:/// ds21227f-page 26 ? 2008 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: http://support.microchip.com web address: www.microchip.com atlanta duluth, ga tel: 678-957-9614 fax: 678-957-1455 boston westborough, ma tel: 774-760-0087 fax: 774-760-0088 chicago itasca, il tel: 630-285-0071 fax: 630-285-0075 dallas addison, tx tel: 972-818-7423 fax: 972-818-2924 detroit farmington hills, mi tel: 248-538-2250 fax: 248-538-2260 kokomo kokomo, in tel: 765-864-8360 fax: 765-864-8387 los angeles mission viejo, ca tel: 949-462-9523 fax: 949-462-9608 santa clara santa clara, ca tel: 408-961-6444 fax: 408-961-6445 toronto mississauga, ontario, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific asia pacific office suites 3707-14, 37th floor tower 6, the gateway harbour city, kowloon hong kong tel: 852-2401-1200 fax: 852-2401-3431 australia - sydney tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing tel: 86-10-8528-2100 fax: 86-10-8528-2104 china - chengdu tel: 86-28-8665-5511 fax: 86-28-8665-7889 china - hong kong sar tel: 852-2401-1200 fax: 852-2401-3431 china - nanjing tel: 86-25-8473-2460 fax: 86-25-8473-2470 china - qingdao tel: 86-532-8502-7355 fax: 86-532-8502-7205 china - shanghai tel: 86-21-5407-5533 fax: 86-21-5407-5066 china - shenyang tel: 86-24-2334-2829 fax: 86-24-2334-2393 china - shenzhen tel: 86-755-8203-2660 fax: 86-755-8203-1760 china - wuhan tel: 86-27-5980-5300 fax: 86-27-5980-5118 china - xiamen tel: 86-592-2388138 fax: 86-592-2388130 china - xian tel: 86-29-8833-7252 fax: 86-29-8833-7256 china - zhuhai tel: 86-756-3210040 fax: 86-756-3210049 asia/pacific india - bangalore tel: 91-80-4182-8400 fax: 91-80-4182-8422 india - new delhi tel: 91-11-4160-8631 fax: 91-11-4160-8632 india - pune tel: 91-20-2566-1512 fax: 91-20-2566-1513 japan - yokohama tel: 81-45-471- 6166 fax: 81-45-471-6122 korea - daegu tel: 82-53-744-4301 fax: 82-53-744-4302 korea - seoul tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 malaysia - kuala lumpur tel: 60-3-6201-9857 fax: 60-3-6201-9859 malaysia - penang tel: 60-4-227-8870 fax: 60-4-227-4068 philippines - manila tel: 63-2-634-9065 fax: 63-2-634-9069 singapore tel: 65-6334-8870 fax: 65-6334-8850 taiwan - hsin chu tel: 886-3-572-9526 fax: 886-3-572-6459 taiwan - kaohsiung tel: 886-7-536-4818 fax: 886-7-536-4803 taiwan - taipei tel: 886-2-2500-6610 fax: 886-2-2508-0102 thailand - bangkok tel: 66-2-694-1351 fax: 66-2-694-1350 europe austria - wels tel: 43-7242-2244-39 fax: 43-7242-2244-393 denmark - copenhagen tel: 45-4450-2828 fax: 45-4485-2829 france - paris tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany - munich tel: 49-89-627-144-0 fax: 49-89-627-144-44 italy - milan tel: 39-0331-742611 fax: 39-0331-466781 netherlands - drunen tel: 31-416-690399 fax: 31-416-690340 spain - madrid tel: 34-91-708-08-90 fax: 34-91-708-08-91 uk - wokingham tel: 44-118-921-5869 fax: 44-118-921-5820 w orldwide s ales and s ervice 01/02/08 downloaded from: http:/// |
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